1. Field of the Invention
The present invention relates to microprocessors and more particularly the generation of clock signals in the microprocessors and the operating modes of the microprocessors.
2. Description of the Related Art
FIG. 1 represents the structure of a classical microprocessor. The microprocessor comprises a central processing unit CPU for performing the program operations in connection with a memory MEM allowing the data and the program instructions to be stored. The operation of the CPU is clocked by a main clock signal CLK coming from a clock generation circuit comprising a quartz X oscillator circuit OSC. A frequency divider circuit PSC (prescaler) lowers the frequency of the signal CKO coming from the oscillator OSC and delivers the main clock signal CK1 that determines the nominal working frequency of the CPU. Another frequency divider circuit DCT is bypass positioned on the line of the main clock signal CK1 to supply another clock signal CK2 of lower frequency than the clock signal CK1. A multiplexer circuit receives the two clock signals CK1, CK2 to apply one of the two selected signals CK1 or CK2 at clock signal input CLK of the CPU.
The central processing unit CPU controls the operation of the oscillator OSC by a control signal HALT applied as an on/off command M/A to the oscillator circuit OSC. When the CPU activates the signal HALT, the oscillator OSC switches off and there is no longer any clock signal, such that the operation of the CPU is interrupted.
At the same time, the signal HALT is applied as a start-up command A/M of an auxiliary automatic wake-up circuit AWUCT (Auto Wake-Up) of the microprocessor. This self-contained circuit AWUCT generally comprises its own oscillator circuit OSCAUX the signal pulses CK3 of which are applied to a counting circuit CNTAWU to generate a signal pulse WUIT at the end of a time interval of predefined duration determining a periodical wake-up time base. The signal WUIT is applied as an interrupt signal to an interrupt decode circuit ITC. The circuit ITC receives, masks and codes the interrupt signals coming from various sources, such as the general start up/shutdown command button ON/OFF (reset interrupt IOIT or RESET) and the time base signal WUIT of the automatic wake-up circuit AWUCT, the only ones represented here.
Classically, these peripheral circuits allow the microprocessor to have several operating modes, with a view to globally reducing the electric current consumption of the circuit.
A microprocessor such as the one in FIG. 1, has a normal operating mode at full power, or mode RUN, a slow operating mode or mode SLOW, and a standby mode or mode ACTIVE HALT.
In the mode RUN, all the circuits of the microprocessor are awakened and operate at the nominal frequency of the main clock signal CK1, thus at full power. The mode RUN has the disadvantage of requiring considerable electric power since all the circuits of the microprocessor are awakened at their nominal frequency, very high (the consumption of an integrated circuit varies essentially according to the switch rate of the transistors).
In the mode SLOW, the CPU runs at the reduced frequency of the secondary clock signal CK2 (sub-multiple of the frequency CK1) such that the current consumption is divided. However, the current consumption remains high since the central processing unit and all the peripheral circuits are active, particularly the quartz oscillator circuit OSC, that is a high consuming item.
The mode HALT is implemented to avoid this excess consumption, when the CPU is in standby, without any particular operation to perform. In this case, the CPU applies the command HALT to the oscillator OSC, which interrupts the clock signals and the operation of the CPU itself. Thus, in the mode HALT, the central processing unit and the peripheral circuits are deactivated to limit the current consumption, except for the auxiliary circuit AWUCT activated by the command HALT, so as to wake up the CPU at regular time intervals to see to the operations to be performed. At the end of each time interval, one pulse of the signal WUIT generates an interrupt IT that “wakes up” the CPU and reactivates its operation in the execution mode RUN.
More precisely, at the time of the pulse WUIT, the oscillator OSC is awakened by the end of the mode HALT and starts to produce the signal CKO again. Upon start up, the establishment of the oscillations of the circuit OSC1 requires a stabilization time. A circuit counts a fixed number N of cycles of the signal CK1 to determine the duration of the stabilization phase. At the end of this phase STAB, the CPU resumes its normal operation in the mode RUN at the rate of the main clock signal CK1.
Upon this wake-up of the CPU in the mode RUN, the CPU scans the inputs/outputs, checks certain states, executes sub-program routines, and determines whether there are any operations to be performed.
In the affirmative, the CPU maintains its operating mode RUN at full power and executes the program of operations to be performed.
In the event that there are no operations to be performed, the CPU returns to the mode HALT by waking up the signal HALT to start a new cycle again.
Therefore, in microprocessors of known type, during the operation in the halt mode HALT, upon each periodical wake-up, the CPU, the clock circuits and all the peripheral circuits must wake themselves up in the execution mode RUN for a certain number of clock cycles, even if it transpires that there are no operations to be performed, which represents an unjustified excess consumption.
The defect of the microprocessors described above is that they require a high number of stabilization cycles upon the wake-up of the main clock circuit and of the CPU. Typically, depending on the models of microprocessor, it is necessary to wait for a duration in the order of 28 to 214 clock cycles (N=256 to 16,384 cycles) to end the stabilization phase of the oscillator, which represents a considerable number of cycles of operations.
Now, the duration of the stabilization time of the quartz precision oscillators used in the clock circuits of the known type microprocessors is inseparable from the degree of precision of the frequency of the oscillations of the clock signal, on which the accuracy of the internal time of the microprocessor depends for example (the higher the degree of precision of the periodicity of a signal is, the longer the time is to establish this periodic signal).
The disadvantage of this state of the art is that the circuits of the oscillator and of the central processing unit consume considerable electric power during this stabilization time, unnecessarily, without performing any operation.
Furthermore, in the case in which the CPU sees, at the end of the stabilization cycle, that there are no operations to be performed, it generates the signal HALT and returns to the halt mode HALT. Therefore, absurdly, the CPU wakes itself up and consumes electric power, in an unjustified manner, during the stabilization cycles, while it transpires that there are no operations to be performed.